As opposed to planar complementary metal oxide semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source and drain and a top source and drain disposed on the fin channel. VFETs are being explored as a viable device option for continued CMOS scaling beyond the 7 nanometer (nm) technology node.
With conventional process flows, the gate length (Lg) of a VFET is primarily controlled by two etch processes. The gate conductor is deposited conformally around the fin followed by (1) an OPL planarization and etch back process (to expose a top of the fin for the top source and drain), and (2) a wet gate metal etch. The gate length is mostly defined at this stage, but subsequent high-κ dry etch and OPL ashing may also have very fine effects on the Lg as well. Such an etch-controlled gate length (Lg) is, however, subject to a large variation including within wafer, wafer-to-wafer, batch-to-batch, tool dependency, and pattern density (i.e., etch micro-loading) effect.
Therefore, VFET fabrication techniques that avoid the above-described etch related variations would be desirable.